Dataflow Compute & Intelligent Compute Architecture

Available

Next Silicon ICA — a native non-Von-Neumann dataflow architecture where computation is driven by data availability rather than a sequential instruction stream.

Overview

Classical Von-Neumann processors spend much of their die area on control logic — branch prediction, out-of-order scheduling, speculation — that contributes nothing to actual computation. The Intelligent Compute Architecture (ICA) takes a different approach: a grid of compute units (ALUs) is wired as a graph; as soon as data arrives at a unit, computation starts automatically and the result flows directly to the next unit.

Crucial for practical use: existing code — C++, Fortran, Python and common CAE applications — runs unmodified. The ICA software identifies compute-intensive sections at runtime and reconfigures the hardware automatically, with no domain-specific language or manual adaptation.

Key Pain Points

Control overhead

Much of the CPU die goes to instruction control rather than computation — a structural efficiency loss on compute-intensive workloads.

Memory bandwidth

Data-intensive simulations are often bandwidth- rather than compute-bound; classical architectures hit the memory wall.

GPU porting effort

GPU acceleration often requires CUDA porting and specialized kernels — an effort that existing CAE codebases avoid.

Energy per result

Data centres hit power limits; performance-per-watt becomes the limiting factor for scaling.

Methods & Fit

Where dataflow execution addresses the pain points above:

Data-driven execution

Eliminates control overhead by letting data availability trigger computation — no speculative scheduling, no branch-prediction unit.

Runtime reconfiguration

The software profiles hot paths during execution and adapts the hardware configuration dynamically — no code rewrite or DSL.

Distributed HBM

Addresses the bandwidth limit through tightly coupled high-bandwidth memory close to the compute units.

Typical workload classes:

Rendering & VFX Seismic (RTM/FWI) Monte Carlo Genomics & Cryo-EM Signal processing Telemetry streams

Roadmap: Sovereign Silicon & Dataflow

Phase	Strategic Action	Outcome
1. ISA Evaluation	RISC-V vector extension mapping for legacy x86 code; Arbel host-CPU assessment.	Migration risk report.
2. Dataflow Mapping	Profiling application hot paths for ICA execution; onboarding unmodified C++/Fortran/Python.	Hotspot-to-dataflow fit report.
3. Adaptive Deployment	Next Silicon Maverick integration with runtime reconfiguration; staged CPU fallback where ISV certification is pending.	Transparent, de-risked acceleration.
4. Compliance Hardening	Root-of-trust audit for the open-source silicon architecture across host and accelerator.	Digital sovereignty & security.

Metrics

up to 10x

performance vs. leading GPUs (vendor-reported)

code rewrites — existing code runs unmodified

Sandia

production reference (National Laboratories)

Vendor figures from Next Silicon; project-specific values are determined in a benchmark audit.

Limitations

ISV certification: commercial CAE solvers (e.g. OpenFOAM, PamCrash distributions) require completed certification; until then the staged CPU-fallback strategy applies.
Ecosystem maturity: toolchain and community are younger than established GPU stacks.
Workload dependence: the benefit is greatest on data-driven, highly parallel workloads; serial, control-heavy loads gain little.

This page assesses technical fit, not a procurement decision.

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