Sovereign RISC-V Silicon

In Evaluation

An open-ISA CPU stack — host and accelerator from the same RISC-V family — free of ARM licensing and architecture-level export-control exposure.

Overview

RISC-V is the only path to a high-performance CPU stack without ARM licensing dependency and without US export-control exposure at the architecture level. For European public bodies, research institutions and sovereign-cloud programmes, this is increasingly an explicit procurement criterion.

With the two most ambitious independent high-performance RISC-V startups (Ventana, Rivos) acquired by hyperscalers in 2025, the number of independent options is shrinking just as the market matures. A RISC-V host such as Arbel — paired with a RISC-V-based accelerator — fills that gap for buyers without their own silicon organisation.

Key Pain Points

Licensing dependency

ARM-based stacks carry per-core royalties and licensing constraints outside the buyer's control.

Export-control exposure

Proprietary architectures can be subject to shifting export regimes; open ISA reduces that risk.

Vendor lock-in

A closed CPU-plus-accelerator stack ties the buyer to a single vendor's roadmap.

Shrinking supply

Hyperscaler acquisitions have removed the leading independent RISC-V CPU options from the open market.

Methods & Fit

Where this architecture addresses the pain points above:

Open ISA host

Arbel provides a server-grade RISC-V host CPU with no ARM royalty and an auditable instruction set.

Single-family stack

Host and accelerator share the RISC-V family, enabling tighter coupling than generic PCIe pairing with a foreign CPU.

Auditable root of trust

Open silicon allows a security audit across host and accelerator that closed IP does not.

Typical workload classes:

Public sector / defence National HPC centres Sovereign cloud ASIC-adjacent hosts Storage appliances Research labs

Roadmap

Phase	Strategic Action	Outcome
1. ISA Evaluation	Assess Arbel host CPU and RISC-V vector extension coverage for existing workloads.	Migration risk report.
2. Reference Platform	Stand up a host-plus-accelerator reference with an ODM partner (e.g. Inventec).	Validated reference design.
3. Sovereign Pilot	Deploy a pilot for a public-sector or national-lab reference customer.	Sovereignty reference case.
4. Compliance Hardening	Root-of-trust audit across host and accelerator.	Digital sovereignty & security.

Metrics

ARM per-core royalties in an open-ISA stack

1 family

host and accelerator from one RISC-V lineage

EU-aligned

fits sovereign-cloud and public-procurement criteria

Limitations

Not yet in production: the Arbel mainboard is designed but not yet manufactured; timelines depend on the vendor roadmap.
Younger ecosystem: the RISC-V server software stack is less mature than established x86/ARM stacks.
Evaluation stage: positioning and fit are assessed per project; this is not a procurement recommendation.

This page assesses technical fit, not a procurement decision.

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